Course Description
How does one make the complex integrated circuits/systems –chips- in your mobile phone? This is a first course on the systematic engineering design principles for complex systems. The course emphasizes hierarchical abstractions of devices, circuits, functional units with a focus on physical design of integrated circuits. It is a Computer Aided Design (CAD) oriented laboratory course where lectures will introduce principles and fundamental concepts. Students working in groups will design and fabricate a CMOS camera integrated circuit.
Professor Andreas G. Andreou, Barton Hall 400B
(410)-516-8361
andreou at jhu dot edu
Professor Pedro Julian, Barton Hall 400B
(410)-516-8361
pedro.julian at gmail dot com
Course Archives | 2015 | 2014 | 2013 | 2012 | 2011 | 2010 | 2009
Syllabus and Handout Notes
Week 1 (1/26)
Handout: Introduction to VLSI systems (pdf); Handout: Making a Chip that Sees (pdf)
Course logistics summary handout (pdf)
Handout for weekly notes taking (pdf)
Reading assignment: Chapter 1 of Sicard/Delmas-Bendhia, Sections (1.1-1.7)
Gordon Moore's original paper on semiconductor scaling -what is Very Large Scale Integration (VLSI) and why it is important- (pdf)
Turning Potential Into Realities: The Invention of the Integrated Circuit (Jack S. Kilby, Nobel Lecture 8 December 2000) (pdf)
Week 2 (2/2)
Handout: MOS devices, technology and design rules (video will be shown in class) (pdf)
How A Chip is Made (animation video)
From Sand to Chips (GlobalFoundries video)
Reading assignment: Chapter 2 of Sicard/Delmas-Bendhia, Sections (2.1-2.12)
S. M. Aziz, E. Sicard, and S. Bendhia, “Effective Teaching of the Physical Design of Integrated Circuits Using Educational Tools,” IEEE Trans Educ, vol. 53, no. 4, pp. 517–531, Nov. 2010. - why we teach this course the way we do- (pdf)
Week 3 (2/9)
Handout: MOS transistor and mathematical models (pdf), Photodetectors (pdf)
The Invention and Early History of the CCD (George E. Smith, Nobel Lecture 8 December 2009) (pdf)
Reading assignment: Chapter 3, Sections (3.1,3.2,3.7) of Sicard/Delmas-Bendhia.
Chapter 11 from Philippe Pouliquen's writeup (pdf).
Week 4 (2/16)
Handout: Digital abstraction: MOS transistor abstraction as a switch (revisited), the inverter (pdf)
Reading assignment: Chapter 4 Sections (4.1,4.2,4.3,4.4,4.5,4.6,4.11,4.13) of Sicard/Delmas-Bendhia
Chapter 1 and 2 from Philippe Pouliquen's writeup (pdf).
Week 5 (2/23)
Handout: Basic and Complex CMOS Gates (pdf)
Reading assignment: Chapter 6, Sections (6.1,6.2,6.3,6.4,6.5,6.6,6.7,6.8,6.9,6.11) of Sicard/Delmas-Bendhia
Chapter 3 and 4 from Philippe Pouliquen's writeup (pdf).
Week 6 (3/1)
Handout: State Holding Elements and Sequential Circuits (pdf)
Reading assignment: A nice introduction to Sequences and State can be found in Ward and Halstead Chapter 4, Sections 4.1 to 4.7 (pdf). The basis of sequential logic circuits is also discussed in Sicard/Delmas-Bendhia Chapter 8, Sections 8.1 to 8.4; application of sequential logic in counters and dividers in Sicard/Delmas-Bendhia Chapter 8, Sections 8.5 to 8.7. Chapter 6 from Philippe Pouliquen's writeup is also a tutorial introduction to the topic (pdf).
Week 7 (3/8 Midterm Examination)
Review and midterm examination, project discussion.
Spring Break
Week 8 (3/22)
Handout: Interconnects - Delay and Energy (pdf)
Reading assignment: Chapter 5, Sections (5.1,5.2,5.3,5.4,5.5,5.6,5.7) of Sicard/Delmas-Bendhia.
Chapter 9 from Philippe Pouliquen's writeup (pdf).
Week 9 (3/29)
Handout: Arithmetic (Half Adders and Adders) Counters and Comparator (pdf)
Reading assignment: Chapter 7, Sections (7.1, 7.2, 7.3, 7.8) in Sicard/Delmas-Bendhia
Week 10 (4/5)
Handout: Tradeoffs in system design, circuit level, architecture level, with applications to arrays of elements (memory and imagers)
(pdf)Week 11 (4/12)
Handout: Analog and interface CMOS Circuits (pdf)
Reading assignment: Chapter 9 in Sicard/Delmas-Bendhia
Week 12 (4/19)
Handout: Data converters (pdf)
Week 13 (4/26)
Project Work
Week 14 (5/3)
Final Project Presentations
Projects
Mini Project: Moore's Law in Your Family (pdf)
Due: February 11th.
Final Project and Report: A Chip That Can See
Due: May 12th (Midnight)
The report must include the following: i) Introduction and overall description of the project, ii) Imager architecture with a DSCH level diagram, iii) Description of the system that you have designed with transistor level diagram of each of the sub-systems. Also discuss the design flow, i.e. how you went from the concept to simulation and layout, iv) Size of pixel, number of pixels in the x and y dimensions, v) Discussion and Conclusions. Report must be no more than 5 pages long. Please print and submit in the ECE office, Barton Hall 105 AND ALSO submit electronically to jhu216@gmail.com.
Collaboration: NO. You can work together as a group on the design of your final project, but the description, discussion, conclusions and preparation of the report must be done on your own. The grade for the final project will be based on your contribution to the team's effort and your final project report i.e. this report.
Laboratory Work
CAD Lab #1: Microwind and DSCH lab exploration: Load AllMosDevices.MSK file explore the physical layout tools and run the cross-section to obtain the cross-section for one of the devices reproducing Fig.24. Load MosN.MSK file and simulate the single device to reproduce the results on Fig. 2.31. Explore using the MOS Generation Tool (section 2.10) to create the layout for an MOS device.
CAD Lab #2: Microwind and DSCH lab exploration: Use the MOS characteristics tool (Fig. 3.4) to get the static characteristics of an NMOS and a PMOS device with model LEVEL=1. Change the threshold voltage and observer how the characteristics change (reproduce something that looks like the data characteristics in Fig. 3.5. Repeat with model LEVEL=3 and LEVEL=BSIM. Why do you think the plots for the different models are different. Using the BSIM model, plot estimate the Ron resistance for both the NMOS and PMOS device.
CAD Lab #3: Microwind and DSCH lab exploration: Design a NAND gate in the standard pitch for logic synthesis.
CAD Lab #4: Microwind and DSCH lab exploration: Explore the the simulation properties for the basic AND and OR operation by loading BaseCMOS.MSK in DSCH and exploring the switching of the different gates. Perform a logic simulation of the 2 input NAND function in DSCH by loading Nand2Cmos.SCH and verifying that truth table is truly true! In microwind explore the silicon compiler by compiling the layout of a 2 input NAND gate (Fig. 6.12). Add simulation properties and perform a simulation of the 2 input NAND gate to obtain something that looks like the results in Fig. 6.20. Starting from DSCH create a gate based 2 input XOR gate (as shown in in Fig 6.53) and save it as myXor2.SCH and then follow the flow to create a verilog description of a gate based 2 input XOR gate and save it as myXor_16.txt, then in microwind load the resultant myXor_16.txt to synthesize the layout. Save it to myXor2_16.msk and do a simulation of the circuit to obtain results that look like Fig. 6.54. (If you are having trouble saving the files load and experiment with the defaults, Xor2.SCH, Xor2_16.TXT, Xor2_16.MSK).
CAD Lab #5: Microwind and DSCH lab exploration: In DSCH draw the schematic of a positive edge flip-flop and generate the corresponding layout in Microwind. Simulate the output using a stream of zeros and ones. Repeat using a negative edge flip-flop. Use the positive edge flip-flop and cascade eight of them by connecting the output of one flip-flop to the input of the next one. Use a common clock signal. Generate a layout and simulate the output using a stream of zeros and ones. Explore the layout options to get a square and rectangular layout.
CAD Lab #6: Microwind and DSCH lab exploration: Use the 2D simulation tool to visualize the electric field lines between the conductor and ground. Experiment with different configurations of interconnects and also distance between the interconnects. Explore the simulation of the interconnect capacitance of various interconnect configurations in 0.18um CMOS technology (Use Table 5.1 to find the size of the metal layers). In microwind load RCModel.MSK and explore the circuit simulation of different interconnect configurations (reproduce results of Fig 5.43).
CAD Lab #7: LTSpice lab exploration: Use LTSpice to explore the simulation of simple circuits. You can get LTSpice here. If you have trouble downloading it from Linear Technology please download (not the latest version) here for Mac OSX and Windows. Start with the simple circuit that demonstrates the abstraction of a transistor into a composite circuit that includes a switch, a linear resistor and a capacitor for the inverter (LTSpice file) and create a circuit that abstracts the behavior of NAND gate in CMOS. Simulate the circuit, experiment with changing the width and lengths of MOS transistors and corresponding values for Ron for PMOS and NMOS devices.