Projects
Mini Project: Moore's Law in Your Family (pdf)
Due: February 7th
Final Project and Report: A Chip That Can See
Due: May 14th (Midnight)
The report must include the following: i) Introduction and overall description of the project, ii) Imager architecture with a DSCH level diagram, iii) Description of the system that you have designed with transistor level diagram of each of the sub-systems. Also discuss the design flow, i.e. how you went from the concept to simulation and layout, iv) Size of pixel, number of pixels in the x and y dimensions, v) Discussion and Conclusions. Report must be no more than 5 pages long. Please print and submit in the ECE office, Barton Hall 105 AND ALSO submit electronically to jhu216@gmail.com.
Collaboration: NO. You can work together as a group on the design of your final project, but the description, discussion, conclusions and preparation of the report must be done on your own. The grade for the final project will be based on your contribution to the team's effort and your final project report i.e. this report.
Laboratory Work
CAD Lab - Basic MOS device: Microwind and DSCH lab exploration: Load AllMosDevices.MSK file explore the physical layout tools and run the cross-section to obtain the cross-section for one of the devices reproducing Fig.24. Submit screenshot to BB. Load MosN.MSK file and simulate the single device to reproduce the results on Fig. 2.31. Submit screenshot to BB. Explore using the MOS Generation Tool (section 2.10) to create the layout for an MOS device. Submit screenshot to BB. Due: February 14th
CAD Lab - MOS device simulation: Microwind and DSCH lab exploration: Use the MOS characteristics tool (Fig. 3.4) to get the static characteristics of an NMOS and a PMOS device with model LEVEL=1. Submit screenshot to BB. Change the threshold voltage and observer how the characteristics change (reproduce something that looks like the data characteristics in Fig. 3.5. Repeat with model LEVEL=3 and LEVEL=BSIM. Submit screenshot to BB. Why do you think the plots for the different models are different. Using the BSIM model, plot estimate the Ron resistance for both the NMOS and PMOS device. Submit your work (how do you estimate Ron) results and discussion to BB. Due: February 21st
Lab - MOS device characterization: (pdf). Collaboration: YES. You can work together in groups of three in the lab but please write up the report on your own, i.e. results and discussion of results. CD4007 datasheet (pdf). Two key references to this lab assignment is the Schichman and Hodges analytical MOS transistor model (LEVEL=1) (pdf) and a paper that discusses in the Appnendix parameter extraction and simulation for transistors in the CA3600 array (same as CD 4007) (pdf). Submit lab report to BB. Due: March 2
CAD Lab - SPICE circuit simulation: LTSpice lab exploration: Use LTSpice to explore the simulation of simple circuits. You can get LTSpice here. If you have trouble downloading it from Linear Technology please download (not the latest version) here for Mac OSX and Windows. Start with the simple circuit that demonstrates the abstraction of a transistor into a composite circuit that includes a switch, a linear resistor and a capacitor for the inverter (LTSpice file) and create a circuit that abstracts the behavior of NAND gate in CMOS. Simulate the circuit, experiment with changing the width and lengths of MOS transistors and corresponding values for Ron for PMOS and NMOS devices. Due: March 2
CAD Lab - Interconnects: Microwind and DSCH lab exploration: Use the 2D simulation tool to visualize the electric field lines between the conductor and ground. Experiment with different configurations of interconnects and also distance between the interconnects. Submit samples of your work to BB ( 3 or 4 screenshots of field plots for various configurations). Explore the simulation of the interconnect capacitance of various interconnect configurations in 0.18um CMOS technology (Use Table 5.1 to find the size of the metal layers). Submit screenshot to BB. In microwind load RCModel.MSK and explore the circuit simulation of different interconnect configurations (reproduce results of Fig 5.43). Submit screenshot to BB. Due: March 7th
CAD Lab - Basic CMOS layout: Microwind and DSCH lab exploration: Design a NAND gate in the standard pitch for logic synthesis. Submit screenshot of layout to BB. Due: March 14th
CAD Lab - Logic Simulation of CMOS Circuits: Microwind and DSCH lab exploration: Explore the the simulation properties for the basic AND and OR operation by loading BaseCMOS.MSK in DSCH and exploring the switching of the different gates. Perform a logic simulation of the 2 input NAND function in DSCH by loading Nand2Cmos.SCH and verifying that truth table is truly true! In microwind explore the silicon compiler by compiling the layout of a 2 input NAND gate (Fig. 6.12). Add simulation properties and perform a simulation of the 2 input NAND gate to obtain something that looks like the results in Fig. 6.20. Submit screenshots of your work to BB. Starting from DSCH create a gate based 2 input XOR gate (as shown in in Fig 6.53) and save it as myXor2.SCH and then follow the flow to create a verilog description of a gate based 2 input XOR gate and save it as myXor_16.txt, then in microwind load the resultant myXor_16.txt to synthesize the layout. Save it to myXor2_16.msk and do a simulation of the circuit to obtain results that look like Fig. 6.54. Submit screenshots of your results to BB. (If you are having trouble saving the files load and experiment with the defaults, Xor2.SCH, Xor2_16.TXT, Xor2_16.MSK). Due: April 4th
Lab - Photodetector characterization: (pdf) Collaboration: YES. You can work together in groups of three in the lab but please write up the report on your own, i.e. results and discussion of results. Submit lab report to BB. Due: April 11th
CAD Lab - Introduction to CADENCE CAD enviornment: Complete the Cadence tutorial here. After you complete the tutorial, do the layout, schematic, LVS and SPICE simulation of a 9 inverter ring oscillator, i.e. a circuit that comprises of nine inverters connected to each other in a loop. Do the simulation at a power supply of 3.3 Volts, 2.5 Volts and 1.2. Volts. Probe the voltage at any point in the inverter chain/loop. Submit to BB screenshots (i) of your circuit, (ii) layout and (iii) SPICE simulation result for the 3 voltage conditions as well as a (iv) discussion on what you observed and why in the results of the simulations at different voltages. Collaboration: YES. You can work together in groups of two to do the tutorial and ring oscillator design but please write up the report on your own, i.e. results and discussion of results. Due: April 18th