Time: Monday, Wednesday, Friday: 11am, Remsen 101
Instructor: Dr. G. Meyer, Barton Hall, Room 105,
e-mail: gglmeyer@jhu.edu
Teaching Assistants:
Anoop Deoras, CSEB Room 321 , e-mail: deoras@jhu.edu
Kang Zhang, Barton Hall, Room 410 , e-mail: kzhang8@jhu.edu
Recommended: Digital Logic Cicuit Analysis & Design, Victor P. Nelson, H. Troy Nagle, Bill D. Carroll, J. David Irwin, Prentice Hall.
Hand out: Problems for Digital System Fundamentals, Version 18,
Hand out: Lab 1: Introduction to the Training Kit and Basic Gates, and Lab 2: Combinational Logic Circuits
Office Hours:
G. Meyer : Tuesday 10-11, Wednesday 10-11, all in Barton Hall Room 105
Anoop Deoras: Monday 10-11; Tuesday 10-3; Wednesday 10-11; Thursday 12-3
in Barton Hall Room 322
Kang Zhang: Monday 12-3; Wednesday 12-3; Thursday 10-12; Friday 12-2
in Barton Hall Room 410
Educational Objectives: Development of the ability to analyze and synthesize combinational and synchronous sequential logic circuits
Grading: HomeWork 10%, Midterm1 15%, Midterm2 30%, Final 45%
Laboratory Session 1: Friday, March 14 , CSEB 224, 11am
Laboratory Session 2: Friday, April 18, CSEB 224, 11 am
Midterm 1: Location: Remsen 101,
Date: Monday, February 25, 2008, ,
Closed Book, 55 minutes (show all work)
MAX: 10; MIN: 3; AVERAGE: 8.2; STDEV: 1.89
Midterm 2: Location: Remsen 101,
Date: Monday, April 7, 2008,
Closed Book, 55 minutes (show all work)
MAX: 10 ; MIN: 4.5 ; AVERAGE: 8.1 ; STDEV: 1.7
Final: Location: Remsen 101,
Date: Wednesday, May 14, Final Start at 2 pm
Closed Book (show all work)
MAX: ; MIN: ; AVERAGE: ; STDEV:
Note 1: Homeworks and midterms not picked up in class may be obtained from the TA's during their office hours.