Department of Electrical and
Computer Engineering
HIGH-SPEED,
DELAY-INSENSITIVE
MODEL-FREE
ADAPTIVE MICROSYSTEMS
Dimitrois Loizos
Graduate Research Assistant
Electrical and Computer Engineering
Several applications in wired, wireless RF and
free-space optical communications call for adaptive compensation of high-speed
variability in propagating media, such as intersymbol interference, multi-path
fading and atmospheric turbulence. The complexity of modeling these highly
dynamical and nonlinear sources of variability precludes the use of
conventional systems identification and optimal control techniques. Speed
requirements for these applications are furthermore prohibitive and require
control architectures amenable to real-time analog or digital implementation.
This dissertation investigates model-free architecture, and its implementation,
for fast adaptive control of a plant with unknown dynamics, using direct
observation of a metric that is further subject to unknown dynamics. The
approach extends previous work on model-free adaptive control to
delay-insensitive estimation of the gradient of the metric from observations
with unknown time delays. The problem of estimating the gradient of the metric
is formulated as a multi-channel parallel coherent detection task in which each
control variable is perturbed by a sinusoidal dither that propagates through
the metric defining a communication channel. The unknown dynamics of the plant
are represented as unknown phase delays for each of the control variable
sinusoidal signals in the metric. These phase delays can be compensated,
without knowledge of the internal dynamics of the plant or metric, leading to
continuous-time delay-insensitive adaptive optimization of the control metric.
Two multi-phase sinusoidal oscillator topologies,
frequency-tunable in several decades, are presented as candidate sinusoidal
dither generators and their performance is evaluated. A circuit topology
suitable for mixed-signal VLSI implementation is introduced that perturbs the
control signals with sinusoidal dithering signals each at a different
frequency. Stability analysis of the topology indicates its convergence
properties and identifies performance trade-offs. An integrated circuit based
on the proposed architecture has been designed and fabricated in a SiGe BiCMOS
process technology. Characterization of the main building blocks of the
architecture has been performed and closed-loop experiments using customizable
metric functions indicate adaptation speeds below 1μs. Delay compensation using a meta-adaptation loop is
demonstrated and delay-insensitivity of the architecture is validated. Finally,
results from integration of the controller in an adaptive optics setup reveal a
1000-fold increase in adaptation speed compared to previous implementations.
2:00 p.m.
FOR DISABILITY INFORMATION
CONTACT:
Candace Abel, (410) 516-7031 cabel@jhu.edu