The Johns Hopkins University

Whiting School of Engineering

Department of Electrical and Computer Engineering

CRISTA: A Low-Power Process-Adaptive Design Methodology for Nano-scaled Circuits

Seminar By

Swaroop Ghosh

Electrical and Computer Engineering

Purdue University

Abstract:

As CMOS approaches the end of the technology roadmap, several new challenges are emerging in the design of integrated circuits such as power, process variation and thermal issues. Increased power and temperature degrades the reliability while process variations may cause parametric failures reducing the yield. In my talk, I will present a novel adaptive design paradigm called CRISTA which achieves robustness with respect to timing failures while simultaneously provides opportunity for aggressive voltage scaling (with no frequency scaling!) for power and thermal management. Our design principle is based on the fact that some critical paths may fail (under process variation and scaled supply voltage) however; the failures can be avoided if we adaptively provide extra computation time to those paths. The design methodology will also ensure such critical path activation is rare and predictable. This design philosophy allows us to gain high power saving and yield by sacrificing negligible throughput loss. The effectiveness of CRISTA is demonstrated by a two-stage pipeline designed in 130nm technology.

We also employed CRISTA at the micro-architectural level for power/temperature adaptation while maintaining high yield. In contrast to conventional techniques, CRISTA design philosophy achieves highly reliable nano-scaled systems while conforming to the specified power/performance envelope.

Short Bio:

Swaroop Ghosh received B.E. degree in electrical engineering from Indian Institute of Technology, Roorkee, India, in 2000 and the M.S. degree from the University of Cincinnati in 2004. Currently, he is a Ph.D. candidate in School of Electrical and Computer Engineering, Purdue University. From 2000 to 2002, he was with Mindtree Technologies Pvt. Ltd., Bangalore, India as a VLSI Design Engineer. He spent the summer of 2006 in Intel's Test Technology group and summer of 2007 in AMD's Design-for-Test group. His research interests include low-power, process tolerant circuit and system design, fault tolerant design and digital testing for nanometer technologies.

Invited by

Faculty Search Committee

Friday, February 15, 2008

11:00 a.m.

Hodson Hall 203

Refreshments will be served at 10:45 a.m.

FOR DISABILITY INFORMATION

CONTACT: Candace Abel (410) 516-7031 cabel@jhu.edu