Time: Monday, Wednesday, Friday: 11am, Remsen 101
Instructor: Dr. G. Meyer, Barton Hall, Room 310,
e-mail: gglmeyer@jhu.edu
Teaching Assistants:
Recommended: Digital Logic Cicuit Analysis & Design, Victor P. Nelson, H. Troy Nagle, Bill D. Carroll, J. David Irwin, Prentice Hall.
Hand out: Problems for Digital System Fundamentals, Version 18,
Hand out: Lab 1: Introduction to the Training Kit and Basic Gates, and Lab 2: Combinational Logic Circuits
Office Hours:
G. Meyer : Tuesday 10-11, Wednesday 10-11, all in Barton Hall Room 310
Educational Objectives: Development of the ability to analyze and synthesize combinational and synchronous sequential logic circuits
Grading: HomeWork 10%, Midterm1 15%, Midterm2 30%, Final 45%
Laboratory Session 1: Friday, March 13 , CSEB 224, 11am
Laboratory Session 2: Friday, April 3, CSEB 224, 11 am
Midterm 1: Location: Remsen 101,
Date: Monday, February 23, 2009, ,
Closed Book, 55 minutes (show all work)
MAX: ; MIN: ; AVERAGE: ; STDEV:
Midterm 2: Location: Remsen 101,
Date: Monday, April 6, 2009,
Closed Book, 55 minutes (show all work)
MAX: ; MIN: ; AVERAGE: ; STDEV:
Final: Location: Remsen 101,
Date: ???
Closed Book (show all work)
MAX: ; MIN: ; AVERAGE: ; STDEV:
Note 1: Homeworks and midterms not picked up in class may be obtained from the TA's during their office hours.