Time: Monday, Tuesday and Wednesday 11am Remsen 101
Instructor: Dr. G. Meyer, Barton Hall, Room 105,
e-mail: gglmeyer@jhu.edu
Teaching Assistants:
Mary Beckman, Barton Hall, Room 403, e-mail: mbeckman@jhu.edu
Lijie Liu, Barton Hall, Room 6, e-mail: ljliu@jhu.edu
Recommended: Digital Logic Cicuit Analysis & Design, Victor P. Nelson, H. Troy Nagle, Bill D. Carroll, J. David Irwin, Prentice Hall.
Hand out: Problems for Digital System Fundamentals, Version 16,
Hand out: Lab 1: Introduction to the Training Kit and Basic Gates, and Lab 2: Combinational Logic Circuits
Office Hours:
G. Meyer : Tuesday 10-11, Wednesday 10-11, all in Barton Hall Room 105
Mary Beckman: Tuesday 12-4, Thursday 1-4, all in Barton Hall Room 403
Lijie Liu: Monday 12-4, Wednesday 1-4, all in Barton 6
Educational Objectives: Development of the ability to analyze and synthesize combinational and synchronous sequential logic circuits
Grading: HomeWork 10%, Midterm1 15%, Midterm2 30%, Final 45%
Laboratory Sessions: Tuesday, February 28 and Wednesday March 1, Barton 123 at 11am
Midterm 1: Location: Remsen 101, Date: Monday, February 27, 2006, , Closed Book, 55 minutes (show all work) MAX:10 ; MIN:1 ; AVERAGE:7; STDEV: 2.1
Midterm 2: Location: Remsen 101, Date: Monday, April 10, 2006, Closed Book, 55 minutes (show all work) MAX: 10 ; MIN: 3; AVERAGE: 7.6; STDEV: 2.16
Final: Location: Remsen 101, Date: Monday, May 15, Final Start at 9am Closed Book (show all work) MAX: ; MIN: ; AVERAGE: ; STDEV:
Note 1: Homeworks and midterms not picked up in class may be obtained from the TA's during their office hours.