Time: Monday, Tuesday and Wednesday 11am Remsen 101
Instructor: Dr. G. Meyer, Barton Hall, Room 223A,
e-mail: gglmeyer@jhu.edu
Teaching Assistants:
Mary Beckman, Barton Hall, Room 008, e-mail: mbeckman@jhu.edu
Sharad Ranjan, Barton Hall, Room 007, e-mail: sharad@jhu.edu
Recommended: Digital Logic Cicuit Analysis & Design, Victor P. Nelson, H. Troy Nagle, Bill D. Carroll, J. David Irwin, Prentice Hall.
Hand out: Problems for Digital System Fundamentals, Version 15,
Hand out: Lab 1: Introduction to the Training Kit and Basic Gates, and Lab 2: Combinational Logic Circuits
Office Hours:
G. Meyer : Monday 10-11, Tuesday 10-11, all in Barton Hall Room 223A
Mary Beckman: Tuesday 12-5, Wednesday 12-4, all in Barton Hall Room 008
Sharad Ranjan: Monday 9-10, 12:30-2 and 3:30-5, Tuesday 9-10, Wednesday 9-10, Thursday 4-5:30, Friday 12-1:30, all in Barton Hall Room 007
Educational Objectives: Development of the ability to analyze and synthesize combinational and synchronous sequential logic circuits
Grading: HomeWork 10%, Midterm1 15%, Midterm2 30%, Final 45%
Laboratory Sessions: Wednesday March 9 and Wednesday March 23, Barton 123
Midterm 1: Location: Remsen 101,
Date: Monday, March 7, 2005, ,
Closed Book, 55 minutes (show all work)
MAX: 100 ; MIN: 63 ; AVERAGE: 94.28; STDEV: 8.18
Midterm 2: Location: Remsen 101,
Date: Monday, April 18, 2005,
Closed Book, 55 minutes (show all work)
MAX: 60; MIN: 25; AVERAGE: 54.4; STDEV: 7.45
Final: Location: Remsen 101,
Date: Monday, May 16, Final Start at 9am
Closed Book, 55 minutes (show all work)
MAX: 100; MIN: 39; AVERAGE: 88.89; STDEV: 16.50