Time: Monday, Tuesday and Wednesday 11am Remsen 101
Instructor: Dr. G. Meyer, Dunning Hall, Room 405,
e-mail: gglmeyer@jhu.edu
Teaching Assistants:
Lijie Liu, Dunning Hall, Room 406, e-mail: ljliu@jhu.edu, Ph: 410-516-4587
Katherine Tsai, Stieff Building, Room 130, e-mail: kattsai@jhu.edu, Ph: 410-516-0746
Recommended: Digital Logic Cicuit Analysis & Design, Victor P. Nelson, H. Rroy Nagle, Bill D. Carroll, J. David Irwin, Prentice Hall.
Hand out: Problems for Digital System Fundamentals, Version 14,
Hand out: Lab 1: Introduction to the Training Kit and Basic Gates, and Lab 2: Combinational Logic Circuits
Office Hours:
G. Meyer : Monday 10-11, Tuesday 10-11, all in Dunning Hall Room 405
Lijie Liu: M 12:30-4:00; Th 9:30-10:30; Th 2:00-5:00; F 9:30-11:30, all in Dunning Hall Room 2
Katherine Tsai: Tu 12:30-4:00; W 12:30-4:00; F 3:00-5:00, all in Dunning Hall Room 2
Educational Objectives: Development of the ability to analyze and synthesize combinational and synchronous sequential logic circuits
Grading: HomeWork 10%, Midterm1 15%, Midterm2 30%, Final 45%
Laboratory Sessions: March 8 and March 22, Barton 123
Midterm 1: Location: Remsen 101,
Date: Monday, March 1, 2004, ,
Closed Book, 55 minutes (show all work)
MAX: 60 ; MIN: 17 ; AVERAGE: 49; STDEV: 8
Midterm 2: Location: Remsen 101,
Date: Wednesday, March 31, 2004,
Closed Book, 55 minutes (show all work)
MAX: 50 MIN: 7 AVERAGE: 39 STDEV: 8
Final: Location: Remsen 101,
Date: May 10, Final Start at 9am
Closed Book, (show all work)
MAX: MIN: AVERAGE: STDEV: