Time: Monday, Tuesday and Wednesday 11am Remsen 101
Instructor: Dr. G. Meyer, Barton Hall, Room 105,
e-mail: gglmeyer@jhu.edu
Teaching Assistants:
Lambert Mathias,
Barton Hall, Room 004, e-mail: lambert@jhu.edu, Ph: 410-516-5409
Brian Brannon, Barton Hall, Room 004, e-mail: bgb@jhu.edu, Ph: 410-516-7215
Recommended: Digital Logic Cicuit Analysis & Design, Victor P. Nelson, H. Rroy Nagle, Bill D. Carroll, J. David Irwin, Prentice Hall.
Hand out: Problems for Digital System Fundamentals, Version 11, Lab1: Introduction to the Ttraining Kit and Basic Gates, and Lab 2: Combinational Logic Circuits
Office Hours:
G. Meyer : Monday 10-11, Tuesday 10-11
Brian Brannon: Tuesday 9-11, Wednesday 9-11, Thursday 9-12, Friday 2-5
Lambert Mathias: Monday 1-5, Tuesday 1-3, Wednesday 1-5
Educational Objectives: Development of the ability to analyze and synthesize combinational and synchronous sequential logic circuits
Grading: HomeWork 8%, Midterm1 8%, Midterm2 18%, Midterm3 28%, Final 38%
Laboratory Sessions: February 10 and 11, Barton 123
Midterm 1: Location: Remsen 101,
Date: Tuesday, March 4, 2003 ,
Closed Book, 55 minutes (show all work)
MAX: 10 ; MIN: 1 ; AVERAGE: 7.87 ; STDEV: 1.98
Midterm 2: Location: Remsen 101,
Date: Tuesday, April 1, 2003
Closed Book, 55 minutes (show all work)
MAX: 10 MIN: 2 AVERAGE: 8.78 STDEV: 1.56
Midterm 3: Location: Remsen 101,
Date: Tuesday April 29 , 2003 ,
Closed Book, 55 minutes (show all work)
MAX: 8 MIN: 3 AVERAGE: 7.3 STDEV:1.01
Final: Location: Remsen 101,
Date: Monday, May 12, 2003, final start at 9am
Closed Book, (show all work)
MAX: 12 MIN 0.5: AVERAGE: 10.65 STDEV: 1.62